1. Field of the Invention
The present invention relates to a test circuit for a microprocessor or the like, and more specifically, relates to a test circuit having a signature register.
2. Description of Related Art
FIG. 1 is a schematic diagram showing an example of the conventional circuit configuration of a multi-input signature register.
In FIG. 1, numeral 1 designates signal lines, numeral 2 designates exclusive-or elements, numeral 3 designates registers, numeral 4 designates feedback taps, numeral 5 designates signature output terminals for outputting a test result, and numeral 6 designates an input terminal of a clock CLK.
The number of the signal lines 1 is n(1.sub.0 through 1.sub.n-1) corresponding to the number of bits n of a test data I(x), and each of them is connected to one input of each of the exclusive-or elements 2(2.sub.0 through 2.sub.n-1). Also, outputs of the respective exclusive-or elements 2.sub.0 through 2.sub.n-1 are inputted to the registers 3.sub.0 through 3.sub.n-1 of D.sub.0 through D.sub.n-1.
Outputs of the registers 3.sub.0 through 3.sub.n-1 (D.sub.0 through D.sub.n-1) are connected to the feedback taps 4.sub.n-1 through 4.sub.0 (P.sub.n-1 through P.sub.0) and inputs of the next-stage exclusive-or elements 2'.sub.n-1 through 2'.sub.1, and become the test result output lines 5.sub.0 through 5.sub.n-1 of a signature output of n bits S(x), respectively.
Each output of the feedback taps 4.sub.n-1 through 4.sub.1 (P.sub.n-1 through P.sub.1) is connected to one input of each of the exclusive-or elements 2'.sub.n-1 through 2'.sub.1, and to the other input of each of the exclusive-or elements 2'.sub.n-1 through 2'.sub.2, each of the next-stage exclusive-or elements 2'.sub.n-2 through 2'.sub.1 is connected in a feedback manner (note that the output of the feedback tap 4.sub.0 (P.sub.0) is connected to 2'.sub.1). Then, the output of the exclusive-or element 2'.sub.n-1 whereto the output of the feedback tap 4.sub.n-1 (P.sub.n-1) is inputted is connected to the other input of the exclusive-or element 2.sub.0 giving an output to the register 3.sub.0 (D.sub.0).
Also, an output string Y(x) of the last-stage register 3.sub.n-1 (D.sub.n-1) is coupled to the feedback tap 4.sub.0 (P.sub.0), and becomes the test result output line 5.sub.n-1.
In addition, each of the registers 3.sub.0 through 3.sub.n-1 is configured as a flip-flop synchronized with the clock CLK input to the clock input terminal 6. Then, as to the presence or absence of a feedback loop from each of the registers 3.sub.0 through 3.sub.n-1, when a set value p.sub.j (i=0 through n-1) of each of the feedback taps 4.sub.n-1 through 4.sub.0 (P.sub.n-1 through P.sub.0) is "1", connection is made and a feedback loop is configured, and when the set value is "0", no connection is made and no feedback loop is configured.
In addition, in the case of p.sub.j ="0", the exclusive-or elements 2'.sub.n-1 through 2'.sub.1, to which the outputs of the feedback taps 4.sub.n-0 through 4.sub.0 are coupled, are not required.
FIG. 2 illustrates a single-input signature register as contrated with the signature register having an n-bit input shown in FIG. 1, but both are the same in principle.
A test data 1(I(x)) coupled as an input to the single-input signature register shown in FIG. 2 is input to the exclusive-or element 2.sub.0 in synchronism with the clock 6 (CLK). Then, it is sequentially operated on using the exclusive-or elements 2; and the flipflops 3;, with the result of each operation being transferred to the next-stage flip-flop 3.
FIG. 2 shows a circuit wherein a division by the following characteristic polynomial is executed. EQU P(x)=x.sup.n +P.sub.n-1 x.sup.n-1 + . . . +P.sub.2 x.sup.2 +p.sub.1 x+p.sub.0 ( 1)
Here, when the value of pj is "1", the connected state is represented, and when the value is "0", the non-connected state is represented, respectively.
The test data I(x) as shown by the following equation (2) is inputted sequentially from a higher-order term to such a circuit. EQU I(x)=i.sub.m x.sup.m + . . . +i.sub.2 x.sup.2 +i.sub.1 x+i.sub.0( 2)
When the original input term first reaches the flip-flop 3.sub.n-1 (D.sub.n-1) (when it becomes "1"), feedback is applied according to the value of P.sub.n-1 through P.sub.o set in each feedback tap 4.
This means that the circuit shown in FIG. 2 performs the following operation. ##EQU1##
Next, when the value of the register is shifted by one and x.sup.n appears, a subtraction is executed, and when x.sup.n does not appear, no subtraction is executed. Such an operation is a division, and it is understood that the circuit shown in FIG. 2 is a division circuit by means of a characteristic polynomial P(x).
Accordingly, the output string Y(x) is equivalent to a quotient Q(x) of the test data I(x) divided by P(x), and a residue R(x) thereof is held in each flip-flop 3. EQU I(x)=Q(x).multidot.P(x)+R(x) (3) EQU Y(x)=Q(x) (4) EQU Where, EQU Quotient:Q(x)=q.sub.m-n x.sup.m-n + . . . +q.sub.2 x.sup.2 +q.sub.1 x+q.sub.0 ( 5) EQU Residue: R(x)=r.sub.n-1 x.sup.n-1 + . . . +r.sub.2 x.sup.2 +r.sub.1 x+r.sub.0 ( 6)
Consideration will now be made of the effect on the value of each flip-flop 3 (register value) when an error string e(x) is contained in the test data I(x).
The error string e(x) is represented by the following equation. EQU e(x)=Qe(x).multidot.P(x)+Re(x) (7)
Therefore, the test data containing an error is represented as follows. EQU I(x)+e(x)=(Q(x)+Qe(x)).multidot.P(x)+(R(x)+Re(x)) (8)
Then, as the register value (signature S(x)) after the quotient (Q(x)+Qe(x)) has been output, the residual (R(x)+Re(x)) containing the error remains. By judging whether or not the signature S(x)=R(x) holds from this, the error can be detected.
However, when e(x) is reducible by P(x), the signature becomes the same as the true value, and therefore the error is missed.
A similar problem exists also in the multi-input circuit shown in FIG. 1. In the FIG. 1 example, the test data has a width of n and a depth of m, and therefore data is input in parallel in synchronism with the clock CLK. Thereafter, the compressed data present as the test result on output lines 5 is compared with correct data, and the presence or absence of an error in the test data is determined.
Since the signature register compresses data for the purpose of reducing the testing time, this produces a high probability of missing an error in the process. This probability of missing an error is referred to as the error missing probability.
In the signature register having the conventional circuit configuration, a primitive polynomial is adopted as a characteristic polynomial to reduce the error missing probability. However, this increases the area occupied by the circuit in the case where an actual circuit is configured on a chip, and as described above, the feedback loop is required to be configured by disposing the exclusive-or elements at positions corresponding to the number of terms. As a consequence the positions of disposition of these elements become irregular, resulting in a complicated circuit design.